Common source EEPROM and flash memory

ABSTRACT

A nonvolatile memory array is arranged as a plurality of rows and columns of memory cell transistors. The sources of the memory cell transistors in each row of the array are electrically coupled together. The control gates of the memory cell transistors associated with a row in the array are coupled to a wordline associated with that row. The drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column. A source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the sources of all memory cell transistors in that row, and a gate coupled to the wordline. An array of split-gate nonvolatile memory cells is also disclosed.

RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.60/244,620, filed Oct. 30, 2000.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor nonvolatile memories.More particularly, the present invention relates to an improved EEPROMand flash memories.

2. The Prior Art

Several types of nonvolatile memory cells have been used in commercialproducts for many years, ranging from EPROM to EEPROM and Flashmemories. See, for example, “IEEE Standard Definitions andCharacterization of Floating Gate Semiconductor Arrays” IEEE Std1005-1998. The cited reference provides a good background of the varioustypes of memory devices that have been produced and provide a list ofthe terms used in this disclosure.

EPROM and Flash memories usually employ a single MOS transistor with twogates stacked on top of each other, the floating gate and the controlgate, and the conductive state of the transistor can be changed byinjecting electrons onto or removing electrons from the floating gate.EEPROM (byte erasable) memories usually are fabricated with separateselect and control gate (such as the FLOTOX cell), although there areexamples of products where a split gate is also used.

The majority of the memory cells either of the stacked or split gatetype, use the so called T layout where the sources of two cells onadjacent rows are mirrored along the center of a common source diffusionline and the sources of the all the memory transistors of the array areconnected to a common terminal. During reading of the selected cell, thenon selected memory transistors belonging to the selected bitline andwhich have been programmed to a conductive state (they conduct currenteven if abs(Vgs)<0) cannot be changed to a nonconductive during the readmode unless the voltage of the non selected wordlines can be set to bebelow V_(ss) (for NMOS cells) or about V_(cc) (for PMOS cells).Generation of these voltages complicates the design of the memories. Asa result an uncontrolled amount of current (hereinafter called leakagecurrent) flows through the selected bitline and the common source,making the correct reading of the state of the selected memorytransistor very difficult.

This problem has been lessened by insuring that the memory transistor isnever erased (for a NMOS cell) or programmed (for a PMOS cell) to anormally on state when the gate-source voltage is zero, or by adding theselect gate to the memory transistor (split gate cell). A normally onMOS device is often called a depletion device.

An array configuration has been presented in U.S. Pat. No. 5,949,718 inwhich the common source of two adjacent rows is connected to twoadditional transistors whose gates are the wordlines of the rows andwhich are connected to a common potential (ground for the arraydescribed). Even without a split gate memory cell, the leakage currentproblem is reduced, but not completely eliminated. The reason is thatwhen reading one cell, the source of the mirrored cell is also grounded.If this cell has been programmed to be normally on, it contributescurrent during reading and this make more difficult for the sensingcircuitry to decide if the selected cell is on or off. The leakageproblem is reduced as compared to the case of conventional arrays, whichuse a common source for the entire array, since the leakage is limitedto one cell only. The solution of the problem is not to erase the memorycell into a normally on state, although in this case more off currentcan be tolerated.

Another problem with a conventional array using a stacked gate cell anda common source is referred to as a “drain turn-on” problem. As anexample, in an array utilizing a NMOS memory cell, applying 6 V on thedrain (the bitline) and 9 V on the wordline does the programming of theselected cell.

The wordline of the non-selected rows is kept at V_(ss), but the drainsof all the cells connected to the selected bitline are biased at 6 V.The capacitive coupling between the drain and the wordline will bringthe potential of the floating gate to value comprised between 0 and 6 V.The actual value depends on the geometry of the cell and can be easilysuch that the non-selected cells are turned on. In this case eachnon-selected cell on the selected bitline is going to draw current andthe total amount of current required for programming is increased.

BRIEF DESCRIPTION OF THE INVENTION

According to one aspect of the present invention, a nonvolatile memoryarray is arranged as a plurality of rows and columns of memory celltransistors. The sources of the memory cell transistors in each row ofthe array are electrically coupled together. The control gates of thememory cell transistors associated with a row in the array are coupledto a wordline associated with that row. The drains of the memory celltransistors in a column of the array are coupled to a bitline associatedwith that column. A source transistor is associated with each row andhas its source coupled to a common source line, its drain coupled to thesource of all memory cell transistors in that row, and a gate coupled tothe wordline.

According to other aspects of the invention, an array of split-gatenonvolatile memory cell is provided. The array is arranged as aplurality of rows and columns of split-gate memory cell transistors. Thesources of the split-gate memory cell transistors in each pair ofadjacent rows of the array are electrically coupled together. Thecontrol gates of the memory cell transistors associated with a row inthe array are coupled to a wordline associated with that row. The drainsof the memory cell transistors in a column of the array are coupled to abitline associated with that column. A source transistor is associatedwith each row and has its source coupled to a common source line, itsdrain coupled to the sources of all memory cell transistors in that row,and a gate coupled to the wordline.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

FIG. 1 is an electrical schematic diagram of a stacked memory arrayaccording to the present invention.

FIG. 2 is a diagram showing an illustrative layout for the array of FIG.1.

FIG. 3 is an electrical schematic diagram of a second memory arrayaccording to the present invention.

FIG. 4 is a diagram showing an illustrative layout for the array of FIG.3.

FIG. 5 is an electrical schematic diagram of an array employing a splitgate cell.

FIG. 6 is a diagram showing an illustrative layout for the array of FIG.5.

FIG. 7 is an electrical schematic diagram of an illustrativeone-time-programmable memory array according to the present invention.

FIGS. 8A through 8C are layout diagrams providing comparisons of memorycells according to the present invention with a prior-art memory cell.

DETAILED DESCRIPTION OF THE INVENTION

Persons of ordinary skill in the art will realize that the followingdescription of the present invention is illustrative only and not in anyway limiting. Other embodiments of the invention will readily suggestthemselves to such skilled persons having the benefit of thisdisclosure.

The memory array configurations described herein completely eliminatethe current leakage problem and the drain turn-on problem associatedwith prior-art memory arrays. In addition, the memory transistors can beprogrammed or erased without restrictions on the threshold voltage (thememory transistor can be set to operate as a depletion device) or thedrain coupling ratio. This improves the cell read current for a givenset of biasing condition during read, as compared to the case where thememory cell cannot be set to operate as a depletion device. Thistranslates into a reduced read access time, or, for a given cellcurrent, it allows the use of a lower power supply voltage.

The memory array configurations disclosed herein can employ either NMOSor PMOS memory cells of the stacked or split gate type. The memory cellsdisclosed herein use well-proven mechanisms for programming and erasingthe cells. All of the array configurations can be used for implementingFlash memories organized in sectors or full-function EEPROM memoriesorganized in bytes. One array configuration will be shown which can beused for implementing single poly EPROM function using a simple PMOStransistor as the memory element.

FIG. 1 is an electrical schematic diagram of the memory array of thenonvolatile memory cell array 10. The nonvolatile memory cell array 10of FIG. 1, is made of NMOS single transistor memory cells including anonvolatile memory transistor 11. These memory cells are similar to theETOX cell developed by Intel. Each nonvolatile memory transistor 11, hasa source 12, a drain 13, a floating gate 14, and a control gate 15.

Wordlines W₀, W₁, . . . W_(2n), W_(2n+1) are used to select half of agiven row of nonvolatile memory transistors 11 of the nonvolatile memorycell array 10. Each of the wordlines W₀, W₁, . . . W_(2n), W_(2n+1)activates a row of control gates 15.

Bitlines, B_(0,0), B_(0,1) . . . B_(0,7) are used to select of a givencolumn of nonvolatile memory transistors 11 of the nonvolatile memorycell array 10. Each of the bitlines, B_(0,0), B_(0,1) . . . B_(0,7)connected to a column of drains 13.

Source, S is used to select the N+ source diffusion common to each rowof nonvolatile memory transistors 11. This is different from a typicalETOX array where the sources of two adjacent rows of transistors aremerged. Each row of NMOS single transistor memory cells 11 of thenonvolatile memory cell array 10 has a source select transistors T₀, T₁,. . . T_(2n), T_(2n+) associated with it. The source select transistorsT₀, T₁, . . . T_(2n), T_(2n+1) selects the N+ diffusion common for a rowof NMOS single transistor memory cells 11. The source select transistorsT₀, T₁, . . . T_(2n), T_(2n+1) source 16, is connect to the source S andthe drain is connect to the row of nonvolatile memory transistor's 11source 12. Each source select transistors T₀, T₁, . . . T_(2n), T_(2n+1)control gate 17 is activated by the Wordlines W₀, W₁, . . . W_(2n),W_(2n+1).

Each memory byte of NMOS single transistor memory cell nonvolatilememory transistors 11 of the nonvolatile memory cell array 10 areisolated within a P-well PW₀, PW₁ . . . PW_(n) creating a well containedmemory byte 19. The P-well can be biased to the appropriate P-wellvoltage V_(pw), by using, for instance, the CMOS inverter 18. The CMOSinverter selects the P-well PW₀, PW₁, . . . PW_(n) via the CMOS invertergate V_(gpw0), V_(gpw1), . . . V_(n) activated to Vcc.

The floating gate 14 of the array nonvolatile memory transistors 11 innonvolatile memory cell array 10 is the memory cell. The erasure,programming and reading of the floating gate 14 of the NMOS singletransistor memory cells 11 in nonvolatile memory cell array 10 is thememory cell voltages as indicated in Table 1. The values of the voltagesindicated in Table 1 are typical of the type of cell, but they may varydepending on the process technology and the geometry of the cell.

As an example, the floating gate 14 (memory cell 0,0) is programmed whenwordline W₀ is at +9 volts, with the rest of the wordlines W₁, . . .W_(2n), W_(2n+1) at 0 volts; and the bitline B₀ is at +6 volts, with therest of the bitlines B_(0,0), B_(0,1) . . . B_(0,7) at 0 volts. Sourceis at 0 volts, V_(gpw0-n) at Vcc, and V_(pw) at 0 volts. The floatinggate 14 (memory cell 0,0) is selectively programmed by Channel HotElectrons (CHE) injected into the floating gate 14 (memory cell 0,0)using the conditions mentioned above and the threshold is raised to apositive value safely above Vcc.

FIG. 2 is an illustrative layout of the memory array of the nonvolatilememory cell array 10 of FIG. 1. In the present invention, thenonvolatile memory cell array 20 of FIG. 2, is made of NMOS singletransistor memory cells or nonvolatile memory transistors 21. Thesememory cells are similar to the ETOX cell developed by Intel. Eachnonvolatile memory transistor 21, has a source 22, a drain 23, afloating gate 24, and a control gate 25.

Wordlines W₀, W₁, . . . W_(2n), W_(2n+1) are used to select half of agiven row of nonvolatile memory transistors 21 of the nonvolatile memorycell array 20. Each of the wordlines W₀, W₁, . . . W_(2n), W_(2n+1)activates a row of control gates 25.

Bitlines, B_(0,0), B_(0,1) . . . B_(0,7) are used to select of a givencolumn of nonvolatile memory transistors 21 of the nonvolatile memorycell array 20. Each of the bitlines, B_(0,0), B_(0,1) . . . B_(0,7)connected to a column of drains 23 via the contact 26.

Source S is used to select the N+ source diffusion common to each row ofnonvolatile memory transistors 21. This is different from a typical ETOXarray where the sources of two adjacent rows of transistors are merged.

The floating gate 24 of the array nonvolatile memory transistors 21 innonvolatile memory cell array 20 is the memory cell. The erasure,programming and reading of the floating gate 24 of the nonvolatilememory transistors 21 in nonvolatile memory cell array 20 is the memorycell voltages as indicated in Table 1. The values of the voltagesindicated in Table 1 are typical of the type of cell, but they may varydepending on the process technology and the geometry of the cell.

The nonvolatile memory cell array 10 shown in FIG. 1, is a stackedP-well selected single nonvolatile memory cell addressable array.Additional columns of source select transistors T₀, T₁, . . . T_(2n),T_(2n+1) can be introduced in the array in order to keep the resistanceof the source diffusion within acceptable limits creating a group ofwell contained memory bytes 19. Multiple columns of source selectiontransistors will require separate addressing not depicted but well knownin the art.

The voltage V_(ss) shown as the bottom rail, indicates the lowestvoltage supplied externally and in the following is considered equal tothe group potential. V_(cc) indicates the operating voltage of thecircuit.

The N+ source diffusion is common to each row of nonvolatile memorytransistors 11. This is different from a typical prior-art ETOX arraywhere the sources of two adjacent rows of transistors are merged. Thesource of each row 12 is connected to the drain 12 of the source selecttransistors T₀, T₁, . . . T_(2n), T_(2n+1). The gate of the sourceselect transistors T₀, T₁, . . . T_(2n), T_(2n+1) of one row is the sameas the wordline W₀, W₁, . . . W_(2n), W_(2n+1) of the row.

The novel nonvolatile memory cell array 10 configuration describedsubstantially eliminates the current leakage and drain turn-on problem,and the memory transistors can be programmed or erased withoutrestriction on the threshold voltage or the drain coupling ratio. Thememory transistor can be set to operate as a depletion device. Thisimproves the cell read current for a given set of biasing conditionduring read, as compared to the case where the memory cell cannot be setto operate as a depletion device. This translates into a reduced readaccess time, or, for a given cell current, it allows the use of a lowerpower supply voltage.

It will be shown that such novel array configuration can use either NMOSor PMOS memory cells, of the stacked or split gate type, using wellproven mechanisms for programming or erasing the cells.

The operation of the array described with reference to FIGS. 1 and 2 issummarized in Table 1.

TABLE 1 Program Erase Terminals c⁻ to FG, cell off c⁻ to P-well, cell onRead W₀ +9 −9 Vcc W₁ 0 0 0 W_(2n) 0 0 0 W_(2n+1) 0 0 0 B₀ +6 float VreadB₁ 0 float 0 B₇ 0 float 0 S 0 float 0 V_(gpw0) Vcc 0 Vcc V_(gpw1---) VccVcc Vcc V_(pw) 0 +7 0

In Table 1 it is assumed that the cell with bitline B₀ and wordline W₀(cell 0,0) is programmed or erased.

In this array, erase is the nonselective operation since all the cellsof one byte 19 (byte erase) or on the entire selected row (sector erase)are erased. It is also assumed, as it is customarily done in Flash orEEPROM arrays with NMOS memory cells, that the programming operation isalways preceded by the erase operation.

Erasing the nonvolatile memory cell (removal of electrons from thefloating gate) occurs as a result of Fowler-Nordheim (FN) tunneling ofelectrons from the floating gate 14 in FIG. 1 and 24 in FIG. 2 to theP-well PW₀, PW₁, . . . PW_(n). This type of erase is usually calleduniform channel erase and is preferred to the other two mechanism whichhave been used, source erase or negative gate source erase. These othererase mechanisms create a significant band-to-band tunneling current.Band-to-band tunneling current has two deleterious effects; it increasesthe amount of current needed for erasing the byte/sector 19, and it alsomay create retention problems caused by injection of hot holes into thefloating gate. Channel erase can be used in this array because afloating P-Well PW₀, PW₁, . . . PW_(n) is used which can be biasedpositively respect to ground. This well configuration is often calledTriple Well.

With the conditions set forth in Table 1, only the first byte of the rowis erased (for byte erase) since the P-Wells PW₀, PW₁, . . . PW_(n) ofall the other bytes on the same row are at ground potential and thevoltage between the floating gate 14 in FIG. 1 and 24 in FIG. 2, and thechannel (9 V * the cell coupling ratio) is not enough for generating anysignificant amount of FN tunneling current.

Channel Hot Electrons (CHE) injected into the floating gate 14 in FIG. 1and 24 in FIG. 2 using the conditions outlined in Table 1 selectivelyprograms the nonvolatile memory cell. The threshold is raised to apositive value safely above V_(cc). This is the mechanism extensivelyused for EPROM and Flash memories. As previously mentioned, there is nocurrent contribution from the non-selected nonvolatile memory cells onthe same bitline B_(0,0), B_(0,1), . . . B_(0,7) during programmingbecause the sources of these nonvolatile memory cells are floating.

Reading of the nonvolatile memory cell is performed under the conditionsdefined in Table 1. The source select transistor T₀, T₁, . . . T_(2n),T_(2n+1), which is a NMOS transistor designed to be an enhancement type,is turned on, bringing the voltage of the common source of the cells ofthat row to a potential close to ground.

As previously noted, when compared with traditional common sourcearrays, the array configuration of FIGS. 1 and 2 has the advantage thatthe erased threshold can be set to a convenient negative value, since,during reading of the selected cell, the other nonvolatile memory cellsconnected to the selected bitline B_(0,0), B_(0,1), . . . B_(0,7),irrespective of their state, cannot contribute any current because theirsources are floating.

The penalty for using this cell as compared to the other arrays is asmall increase of the vertical dimension of the nonvolatile memory cell,as it will be shown later.

The worst-case maximum voltage that the memory transistor has to sustainis +6 V on the drain side 13 in FIG. 1 and 23 in FIG. 2 with thewordline W₀, W₁, . . . W_(2n), W_(2n+1) grounded (unselected nonvolatilememory cells on the selected bitline B_(0,0), B_(0,1), . . . B_(0,7)).The source select transistor T₀, T₁, . . . T_(2n), T_(2n+1) has to beable to sustain reliably +/−9 V between the gate and the source, drainand body terminals. For good reliability the maximum field across thegate oxide has to be kept below 6 mV/cm, which requires a gate oxidethickness of ˜150 A. The voltage on the junctions of these transistorsis limited to 6 V.

The well-select CMOS transistors 18 have to sustain +7 V between anyterminals. Therefore, in addition to the memory device, enhancement typeCMOS devices with ˜150 A gate oxide need to be available for the sourceselect transistor T₀, T₁, . . . T_(2n), T_(2n+1) and for switching theP-wells PW₀, PW₁, . . . PW_(n). The voltages, which the junctions haveto sustain, are below 10 V and these sustaining voltages can be obtainedwith the junction usually formed for making logic CMOS devices down to0.25 um technologies.

The process flow outlined below assumes that the nonvolatile memory cellarray and the peripheral circuits are embedded in a digital product madewith a conventional CMOS process used for digital products (hereinafterthe “Logic Process”), to which the process steps required by thenonvolatile memory cell transistors and the high voltage devices areadded.

For the present discussion, it is assumed that the Logic Process employsthe so-called retrograde well approach as first introduced in the 0.35um technology node and bulk P-type starting material is used. Whenretrograde wells are used, it is very difficult to use the logicretrograde wells for the nonvolatile devices because of the differentrequirements for threshold voltages and maintaining voltages. It istherefore assumed that the logic wells and the wells used for thenonvolatile memory cell devices are different.

Under these assumptions the Logic Process and the added steps are shownbelow.

Logic Process Stop Added Step Oxide Isolation Deep N-Well formation(Mask #1) High Voltage P-Well formation (Mask #2) Tunnel oxidation(90-100 A) Floating Gate deposition and doping ONO formation FloatingGate patterning (Mask #3) High Voltage Gate oxidation (adjusted for afinal thickness after Logic Gate oxidation of (˜150 A) Logic P-Wellformation Logic N-Well formation Selective removal of High Voltage Gateoxide (Mask #4) Logic Gate oxidation Logic Gate deposition Logic Gatepatterning Stacked Gate patterning and etch (Mask #5) Continue LogicProcess steps

As can be seen from the above process summary, only 5 masking operationsare added to the standard Logic Process.

In the array described with reference to FIGS. 1 and 2, only one sourceselect transistors T₀, T₁, . . . T_(2n), T_(2n+1) per row is used andthe memory byte 19 or sector selection is accomplished using CMOSinverter 18 to biases the separate P-Wells PW₀, PW₁, . . . PW_(n).

Referring to FIG. 1, a memory byte 19 is separated by P-Wells PW₀, PW₁,. . . PW_(n) with memory byte 19 selection being accomplished by using aCMOS inverter 18. Referring now to FIG. 3, memory byte 39 selection isaccomplished using a multiple of source selection S₀, . . . S_(n)replacing the need for the P-wells PW₀, PW₁, . . . PW_(n) of FIG. 1.Accordingly, in a second embodiment, the multiple source selectionnonvolatile memory cell array 30 of FIG. 3, is made of nonvolatilememory transistors 31. The multiple of source selection S₀ . . . S_(n)are used for memory byte 39 or sector selection.

With the multiple of source selection S₀ . . . S_(n) used for eachmemory byte 39 or sector selection, the entire array can be placed on acommon well which does not have to be electrically isolated from thesubstrate.

FIG. 3 is an electrical schematic diagram of the multiple sourceselection nonvolatile memory cell array 30. Each nonvolatile memorytransistors 31, has a source 32, a drain 33, a floating gate 34, and acontrol gate 35.

Wordlines W₀, W₁, . . . W_(2n), W₂₊₁ are used to select half of a givenrow of nonvolatile memory transistors 31 of the multiple sourceselection nonvolatile memory cell array 30. Each of the wordlines W₀,W₁, . . . W_(2n), W_(2n+1) activates a row of control gates 35.

Bitlines, B_(0,0), B_(0,1) . . . B_(0,7) are used to select of a givencolumn of nonvolatile memory transistors 31 of the multiple sourceselection nonvolatile memory cell array 30. Each of the bitlines,B_(0,0), B_(0,1) . . . B_(0,7) connected to a column of drains 35.

The multiple of source selection S₀ . . . S_(n), are used to select theN+ source diffusion common to each row of nonvolatile memory transistors31. This is different from a typical ETOX array where the sources of twoadjacent rows of transistors are merged. Each row of nonvolatile memorytransistors 31 for each memory byte 39 of the multiple source selectionnonvolatile memory cell array 30 has a source select transistorsT_(0,0), T_(0,1) . . . T_(n,0), _(n,2n+1) associated with it. The sourceselect transistors T_(0,0), T_(0,1), . . . T_(n,0), T_(n,2n+1) selectsthe N+ diffusion common for a row of NMOS single transistor memory cells31 for each memory byte 39. The source select transistors T_(0,0),T_(0,1), . . . , T_(n,0), T_(n,2n+1) source 36, is connect to themultiple source selection S₀ . . . S_(n) and the drain is connect to therow of nonvolatile memory transistor's 31 source 32. Each source selecttransistors T_(0,0), T_(0,1), . . . T_(n,0), T_(n,2n+1) control gate 37is activated by the Wordlines W₀, W₁, . . . W_(2n), W_(2n+1).

Each memory byte 39 of nonvolatile memory transistors 31 of the multiplesource selection nonvolatile memory cell array 30 are isolated by themultiple source selection S₀ . . . S_(n).

The floating gate 34 of the array NMOS single transistor memory cells 31in multiple source selection nonvolatile memory cell array 30 is thememory cell. The erasure, programming and reading of the floating gate34 of the nonvolatile memory transistors 31 in the multiple sourceselection nonvolatile memory cell array 30 is the memory cell voltage asindicate in Table 2. The values of the voltages indicated in Table 2 aretypical of the type of cell, but they may vary depending on the processtechnology and the geometry of the cell.

As an example, the floating gate 34 (memory cell 0,0,0 S₀, W₀, B_(0,0))is programmed when wordline W₀ is at +9 volts, with the rest of thewordlines W₀ . . . W_(2n), W_(2n+1) at 0 volts and the bitline B_(0,0)is at +6 volts, with the rest of the bitlines B_(0,0), . . . B_(0,7) at0 volts, multiple source selection S₀ is at 0 volts and the rest of themultiple source selection S₀ . . . S_(n)float. The floating gate 34(memory cell 0,0,0) is selectively programmed by Channel Hot Electrons(CHE) injected into the floating gate 34 (memory cell 0,0,0) using theconditions mentioned above and the threshold is raised to a positivevalue safely above V_(cc).

FIG. 4 is an illustrative layout of the multiple source selectionnonvolatile memory cell array 40 of FIG. 3. In a second embodiment ofthe present invention, the multiple source selection nonvolatile memorycell array 40 of FIG. 4, is made of NMOS single transistor memory cells41. The circuit of FIG. 4 is similar to circuit of FIG. 2 with thedifferences note below.

The multiple of source selection S₀ . . . S_(n), are used to select theN+ source diffusion common to each row of NMOS single transistor memorycells 41. This is different from a typical ETOX array where the sourcesof two adjacent rows of transistors are merged. Each row of NMOS singletransistor memory cells 41 for each memory byte 49 of the multiplesource selection nonvolatile memory cell array 40 has a source selecttransistors T_(0,0), . . . T_(0,1), T_(n,0), T_(n,2+1), associated withit. The source select transistors T_(0,0), T_(0,1), . . . T_(n,0),T_(n,2n+1) selects the N+ diffusion common for a row of NMOS singletransistor memory cells 41 for each memory byte 49.

Each memory byte 49 of nonvolatile memory transistors 41 of the multiplesource selection nonvolatile memory cell array 40 are isolated by themultiple source selection S₀ . . . S_(n).

The novel multiple source selection nonvolatile memory cell array 40configuration described herein substantially eliminates the currentleakage and drain turn-on problem, and the memory transistors can beprogrammed or erased without restrictions on the threshold voltage orthe drain coupling ratio. The memory transistor can be set to operate asa depletion device. This improves the cell read current for a given setof biasing condition during read, as compared to the case where thememory cell cannot be set to operate as a depletion device. Thistranslates into a reduced read access time and/or for a given cellcurrent, it allows the use of a lower power supply voltage.

It will be shown that such novel array configuration can use either NMOSor PMOS memory cells, of the stacked or split gate type, using wellproven mechanisms for programming or erasing the cells.

The operation of the array described with reference to FIGS. 1 and 2 issummarized in Table 2.

The operation of the array of FIGS. 3 and 4 is summarized in Table. 2.

TABLE 2 Program Erase Terminals c⁻ to FG, cell off c⁻ to P-well, cell onRead W₀ +9 Vt+ Vcc W₁ 0 0 0 W_(2n) 0 0 0 W_(2n+1) 0 0 0 B_(0,0) +6 floatVread B_(0,1) 0 float 0 B_(0,7) 0 float 0 S₀ 0 12 0 S_(n) float float 0

In Table 2 it is assumed that the cell with source S₀, bitline B_(0,0)and wordline W₀ (cell 0,0,0) is read, programmed or erased. The valuesof the voltages indicated in Table 2 are typical for this type of cell,but they may vary depending on the process technology and the geometryof the cell.

In this array, erase is the non-selective operation since all the cellsof one byte (byte erase) or on the entire selected row (sector erase)are erased. It is also assumed, as it is customary in Flash or EEPROMarrays with NMOS memory cells, that the programming operation is alwayspreceded by the erase operation.

Erase of the cell (removal of electrons from the floating gate 34)occurs as a result of FN tunneling from the floating gate to the source.This type of erase is done using the so-called grounded gate sourceerase mechanism, which has been widely used for Flash memories. V_(s+)indicates a voltage slightly above the threshold of the source selecttransistor. This type of erase has several drawbacks, as mentionedbefore. In addition a dedicated source junction has to be fabricatedwhich complicates the process.

With the conditions of Table 2, only the first byte of the row is erased(byte erase) since the sources of all the other bytes are floating. Thecell is selectively programmed by CHE as before.

Reading of the cell is done under the conditions defined in Table 2.Again it is clear that no leakage current problem exist during readingbecause the source select transistor of the mirrored cell is off. As aresult the erased threshold of this cell can be set negative.

The array described with reference to FIGS. 3 and 4 does not requireisolated P-Wells, which simplifies the process. Due to the lack of aP-well for the source junctions as in FIG. 1, a specially designedsource junction is used. The junction is a grounded gate source arraymechanism as well known in the art and is an IEEE standard.

In addition, the use of the grounded gate source erase mechanismincreases the current required. The sustaining voltage requirement forthe junction is also higher (12 V vs. 9 V).

A third embodiment of the present invention is shown in FIG. 5, theelectrical schematic diagram of a split gate nonvolatile memory cellarray 50. The split gate nonvolatile memory cell array 50 circuitdepicted in FIG. 5 is similar to the nonvolatile memory cell array 10circuit depicted in FIG. 1 with the differences note below.

Split gate nonvolatile memory cell array 50 is made of split gatenonvolatile memory transistors 51. Each split gate nonvolatile memorytransistor 51, has a source 52, a drain 53, a floating gate 54, and acontrol gate 55.

Wordlines W₀, W₁, . . . W_(2n), W_(2n+1) overlap the floating gate 54 ontwo sides or one side only (as shown later in FIG. 8c, split gate memorycell layout). In the split gate nonvolatile memory transistor 51 theoperation of the wordline over the diffusion area is called the memoryselect 69 or FIG. 6. Each of the wordlines W₀, W₁ . . . W_(2n), W_(2n+1)activates a row of control gates 55.

Source, S is used to select the N+ source diffusion common to each rowof split gate nonvolatile memory transistor 51. Each row of split gatenonvolatile memory transistor 51 of the split nonvolatile memory cellarray 50 has a source select transistors T₀, T₁, . . . T_(2n), T_(2n+1),associated with it. The source select transistors T₀, T₁, . . . T_(2n),T_(2n+1) selects the N+ diffusion common for a row of split gatenonvolatile memory transistor 51. The source select transistors T₂, T₁,. . . T_(2n), T₂₊₁ source 56, is connect to the source S and the drainis connect to both mirrored rows of split gate nonvolatile memorytransistors 51 source 52. Each source select transistors T₀, T₁, . . .T_(2n), T_(2n+1) control gate 57 is activated by the wordlines W₀, W₁, .. . W_(2n), W_(2n+1).

The N+ source diffusion is now shared by two rows of mirrored split gatenonvolatile memory transistors 51 and is connected to one side of thesource select transistors T₀, T₁, . . . T_(2n), T_(2n+1). This saving incell height is compensated by the need to have a wider wordline on thememory cell.

The definition of the wordlines of the memory cells can be done with thepatterning step of the logic gates and the complex patterning step ofthe stacked gate is avoided.

The floating gate 54 of the array split gate nonvolatile memorytransistor 51 in split gate nonvolatile memory cell array 50 is thememory cell. The erasure, programming and reading of the floating gate54 of the split gate nonvolatile memory transistor 51 in split gatenonvolatile memory cell array 50 is the memory cell voltages as indicatein Table 3. The values of the voltages indicated in Table 3 are typicalof the type of cell, but they may vary depending on the processtechnology and the geometry of the cell. As an example, the floatinggate 54 (memory cell 0,0) is programmed when wordline W₀ is at +9 volts,with the rest of the wordlines W₁, . . . W_(2n), W₂₊₁ at 0 volts and thebitline B₀ is at +6 volts, with the rest of the bitlines B_(0,0),B_(0,1) . . . B_(0,7) at 0 volts, Source is at 0 volts, V_(gpw0-n) atVcc and V_(pw) at 0 volts. The floating gate 54 (memory cell 0,0) isselectively programmed by Channel Hot Electrons (CHE) injected into thefloating gate 54 (memory cell 0,0) using the conditions mentioned aboveand the threshold is raised to a positive value safely above Vcc.

FIG. 6 is an illustrative layout of the memory array of the split gatenonvolatile memory cell array 50 of FIG. 5. In a third embodiment of thepresent invention, the split gate nonvolatile memory cell array 60 ofFIG. 6, is made of split gate NMOS single transistor memory cells orsplit gate nonvolatile memory transistors 61. The split gate nonvolatilememory cell array 60 circuit depicted in FIG. 6 is similar to thenonvolatile memory cell array 20 circuit depicted in FIG. 2 with thedifferences note below.

The split gate nonvolatile memory cell array 60 is made of split gatenonvolatile memory transistors 61. Each split gate nonvolatile memorytransistor 61, has a source 62, a drain 63, a floating gate 64, and acontrol gate 65.

Wordlines W₀, W₁, . . . W_(2n), W_(2n+1) overlap the floating gate 64 ontwo sides or one side only (as shown later in FIG. 8c, split gate memorycell layout). In the split gate nonvolatile memory transistor 61 theportion of the wordline over the diffusion area is called the memoryselect 69. Each of the wordlines W₀, W₁, . . . W_(2n), W_(2n+1),activates a row of control gates 65.

The N+ source diffusion is now shared by two rows of mirrored split gatenonvolatile memory transistor 61 and is connected to one side of thesource 62. This saving in cell height is compensated by the need to havea wider wordline on the memory cell.

The definition of the wordlines of the memory cells can be done with thepatterning step of the logic gates and the complex patterning step ofthe stacked gate is avoided.

Since negative bias is needed for erasure, a triple well process isused.

The floating gate 64 of the array of split gate nonvolatile memorytransistors 61 in split gate nonvolatile memory cell array 60 is thememory cell. The erasure, programming and reading of the floating gate64 of the split gate nonvolatile memory transistors 61 in split gatenonvolatile memory cell array 60 is the memory cell voltages as indicatein Table 3.

The novel split gate nonvolatile memory cell array 60 configurationdescribed completely eliminates the current leakage problem and thedrain turn-on problem and the memory transistors can be programmed orerased without restrictions on the threshold voltage or the draincoupling ratio. The memory transistor can be set to operate as adepletion device. This improves the cell read current for a given set ofbiasing condition during read, as compared to the case where the memorycell cannot be set to operate as a depletion device. This translatesinto a reduced read access time, or, for a given cell current, it allowsthe use of a lower power supply voltage.

It will be shown that such novel array configuration can use either NMOSor PMOS memory cells, of the split gate type, using well-provenmechanisms for programming or erasing the cells.

The operation of the array is summarized in Table. 3

TABLE 3 Program Erase Terminals c⁻ to FG, cell off c⁻ to P-well, cell onRead W₀ +9 −9 Vcc W₁ 0 0 0 W_(2n) 0 0 0 W_(2n+1) 0 0 0 B₀ +6 float VreadB₁ 0 float 0 B₇ 0 float 0 S 0 float 0 V_(gpw0) Vcc 0 Vcc V_(gpw1---) VccVcc Vcc V_(pw) 0 +7 0

In Table 3 it is assumed that the cell with bitline B_(0,0), andwordline W₀ (cell 0,0 is programmed or erased. The values of thevoltages indicated in Table 3 are typical for this type of cell, butthey may vary depending on the process technology and the geometry ofthe cell.

In this array, erase is the non-selective operation since all the cellsof one byte (byte erase) or on the entire selected row (sector erase)are erased. It is also assumed, as it is customarily done in Flash orEEPROM arrays with NMOS memory cells, that the programming operation isalways preceded by the erase operation.

Erase of the cell (removal of electrons from the floating gate 54) isassumed to occur as a result of FN tunneling from the floating gate 54to the P-well PW₀, PW₁, . . . PW_(n) as for the split gate array.

With the conditions of Table 3 both the source S and split gatenonvolatile memory transistors 51 in FIG. 5 and 61 in FIG. 6 are turnedoff and the selected P-well PW₀, PW₁, . . . PW_(n) is accumulated. Onlythe first byte of the row is erased (byte erase) since the P-wells PW₀,PW₁, . . . PW_(n) of all the other bytes on the same row are at groundpotential and the voltage between the floating gate 54 in FIG. 5 and 64in FIG. 6 and the channel (9 V * the cell coupling ratio) is not enoughfor generating any significant amount of FN tunneling current.

The cell is selectively programmed using CHE injected into the floatinggate 54 in FIG. 5 and 64 in FIG. 6 using the conditions of Table 3, andthe threshold is raised to a positive value safely above Vcc. This isthe same mechanism used in the stacked gate cell.

Reading of the cell is done under the conditions defined in Table 3. Thesource select transistor T₀, T₁, . . . T_(2n), T_(2n+1), which is a NMOStransistor designed to be an enhancement type, is turned on bringing thevoltage of the common source of the cells of that row close to ground.

As for the split gate array, the erased threshold can be set to aconvenient negative value, since, during reading of the selected cell,the other cells connected to the selected bitline B_(0,0), B_(0,1), . .. B_(0,7), irrespective of their state, cannot contribute any currentbecause their sources are floating.

The high voltage requirements for the array of this embodiment are thesame as for the stacked gate cell array, with one major difference.During erase the memory select transistor has 16 V across its gate andfor reliability reason an oxide thickness of at least 250 A has to beused. The source select transistor T₀, T₁, . . . T_(2n), T_(2n+1) has tobe able to sustain reliably only 6 V on the junction with the gategrounded.

For process simplicity, the gate oxide thickness of the source S andsplit gate nonvolatile memory transistors 51 in FIG. 5 and 61 in FIG. 6may be the same (250 A for the voltages used). The stacked gate arraydescribed before uses a much thinner gate oxide on the source selecttransistor T₀, T₁, . . . T_(2n), T_(2n+1) and the peripheral highvoltage transistors. In this respect it is expected that a larger readcurrent can be obtained on the stacked gate array as compared to thesplit cell. The main limitation is caused by the presence of the memoryselect transistors and its relatively thick gate oxide.

The main advantage of using the cell of split gate nonvolatile memorytransistors 51 in FIG. 5 and 61 in FIG. 6 is the elimination of thestacked gate patterning step in the process, since the same mask andetch used for defining the logic gates can be used to define the memorywordlines. If a lower cell read current can be tolerated, it is easierto integrate these memory arrays into logic CMOS process.

According to another illustrative embodiment of the invention, an arrayof memory cells uses PMOS memory cells. The electrical schematic diagramof the array is the same as shown in FIG. 1 and the layout as in FIG. 2,but the memory cells are stacked gate PMOS cell and are built onisolated N-Wells instead of P-Wells. The source select transistors arePMOS devices.

The operation of the array is summarized in Table. 4.

TABLE 4 Program Erase Terminals c⁻ to FG, cell on c⁻ to N-well, cell offRead W₀ Vgp −8 Vss W₁ +6 +8 Vcc W_(2n) +6 +8 Vcc W_(2n+1) +6 +8 Vcc B₀ 0float Vread B₁ float float 0 B₇ float float 0 S +6 float Vcc V_(gpw0) 00 Vss V_(gpw1---) Vcc Vcc Vcc V_(pw) +6 +8 Vcc

In Table 4, it is assumed that the cell with bitline B_(0,0) andwordline w₀ (cell 0,0) is programmed or erased. The values of thevoltages indicated in Table 4 are typical for this type of cell, butthey may vary depending on the process technology and the geometry ofthe cell.

In a PMOS array programming of the cell (injection of electrons into thefloating gate) lowers the threshold of the cell as compared with thevalue of a cell after UV erase (no charges on the floating gate) and thecell become more conductive.

Erasing increases the threshold setting the cell off during the readoperation. In this array the erase is the non-selective operation (allthe cells of one row or of one byte are simultaneously erased).Programming is the selective operation (only one cell is programmed).The proposed mechanisms for programming and erasing are well known inthe art.

It is also assumed, as it is customarily done in Flash or EEPROM arrayswith PMOS memory cells, that the programming operation is alwayspreceded by the erase operation.

Erase occurs by FN tunneling of electrons from the floating gate underthe selected row to the channel (channel erase). Under the biasconditions of Table 4 the channels of the memory gates under theselected row are inverted and at the same potential of the N-well. Ifbyte erase is desired, the wordlines of the non-selected bytes areeither at −8 or 8 V and the non-selected wells are grounded. For thesebytes the voltage available between the floating gate and the channel (8V * the coupling ratio to the channel) is too low for FN tunneling.

Programming of the cell (injection of electrons into the floating gate)occurs as a result of hot electrons injection into the floating gategenerated by impact ionization of holes moving from the source to thedrain. V_(gp) indicates a voltage usually comprised between 0 and 3 V.It is tuned for maximum electron injection efficiency and is processdependent. Although the cell to be programmed is initially in anon-conductive state, it has been shown that efficient electroninjection occurs if the source-drain bias is above the punch-throughvoltage of the cell, which is dependent on the channel length of thememory transistor.

The cell can be programmed to a normally on state since during the readoperation the non selected bitlines B_(0,0), B_(0,1), . . . B_(0,7) ofthe selected byte are at the same potential of the source S and thesources of the non selected rows are floating (source select transistoris turned off). This is the same as for the NMOS array.

During programming, the worst-case maximum voltage that the memorytransistor has to sustain between source and drain is 6 V with Vgs=Vgpfor the selected cells. During erase there are no high voltages on thememory junctions.

The source select transistor has to be able to sustain reliably +/−8 Vbetween the gate and the source, drain and body terminals. For thereason stated before, a gate oxide thickness of ˜130 A is adequate. Thewell select CMOS transistors have to sustain +8 V between any terminals.In addition to the memory device, enhancement type CMOS devices with˜130 A gate oxide need to be available. The high voltage requirementsfor this array are very low and within the capabilities of the logicsource drain diffusions down to 0.18 um level of scaling.

The process flow described herein for fabricating the NMOS cells can beused for fabricating the arrays with the PMOS cells. The Deep N-wellstep can in principle be omitted, but the designs of the peripheralcircuits which use negative bias usually requires a P-well, which can gonegative below ground. Using the logic N-well for isolating the P-wellis quite a difficult task.

Therefore, also in this case these arrays can be fabricated using astandard Logic Process with the addition of 5 masking operationsdescribe before.

The same array configuration described in FIGS. 3 and 4 can be used byreplacing the stacked NMOS memory cell with the PMOS cell and byswitching the polarity of the wells.

As before it is assumed that a source select transistor is used on eachbyte.

TABLE 5 Program Erase Terminals c⁻ to FG, cell on c⁻ to N-well, cell offRead W₀ +3 −8 Vss W₁ +6 +8 Vcc W_(2n) +6 +8 Vcc W_(2n+1) +6 +8 VccB_(0,0) 0 float Vread B_(0,1) float float 0 B_(0,7) float float 0 S₀ +6+8 Vcc S_(n) 0 0 0

Erase occurs by FN tunneling of electrons from the floating gate underthe selected row to the channel (channel erase). Under the biasconditions of Table 6 the channels of the memory gates under theselected row are inverted and at the same potential of the N-well. Onlythe sources of memory cell, source S₀, bitline B_(0,0) and wordline W₀(cell 0,0,0) are at 8 V. It can be easily seen that the sources of allthe other bytes are floating either because the source selecttransistors are turned off or the source lines are floating. The valuesof the voltages indicated in Table 5 are typical for this type of cell,but they may vary depending on the process technology and the geometryof the cell.

Programming of the cell (injection of electrons into the floating gate)occurs as a result of hot electrons injection into the floating gategenerated by impact ionization of holes moving from the source to thedrain as for the stacked gate PMOS array described before.

High voltage requirements are the same as for the stacked gate PMOSarray and also the process complexity is the same.

The electrical schematic diagram of the array is the same as shown inFIG. 5 and the layout as in FIG. 6, but split gate PMOS cells, built onisolated N-Wells instead of P-Wells, are used. The source selecttransistors are PMOS devices.

The operation of the array is summarized in Table 6.

TABLE 6 Program Erase Terminals c⁻ to FG, cell on c⁻ to N-well, cell offRead W₀ Vgp −8 Vss W₁ +6 +8 Vcc W_(2n) +6 +8 Vcc W_(2n+1) +6 +8 Vcc B₀ 0float Vread B₁ float float 0 B₇ float float 0 S +6 float Vcc V_(gpw0) 00 Vss V_(gpw1---) Vcc Vcc Vcc V_(pw) +6 +8 Vcc

Erasing occurs by FN tunneling of electrons from the floating gate underthe selected row to the channel. The values of the voltages indicated inTable 6 are typical for this type of cell, but they may vary dependingon the process technology and the geometry of the cell.

Under the bias conditions shown in Table 6, both the source S and memoryselect transistors under the selected row are turned on and at the samepotential of the N-well. If byte erase is desired, the bitlines B_(0,0),B_(0,1), . . . B_(0,7) of the non-selected bytes are at ground potentialas the wells. For these bytes the voltage available between the floatinggate 54 in FIG. 5 and 64 in FIG. 6 and the channel (8 V * the couplingratio to the channel) is too low for EN tunneling.

Programming of the cell (injection of electrons into the floating gate54 in FIG. 5 and 64 in FIG. 6) occurs as a result of hot electronsinjection into the floating gate 54 in FIG. 5 and 64 in FIG. 6 generatedby impact ionization of holes moving from the source to the drain as forthe stacked gate PMOS cell. The source S and memory select transistorsunder the selected row are turned on and the memory cell is designed toreach punch-through. It is also assumed, as it is customarily done inFlash or EEPROM arrays with PMOS memory cells, that the programmingoperation is always preceded by the erase operation.

The cell can be programmed to a normally on state since during the readoperation, the memory select transistor of the mirrored cell is turnedoff, the memory cells on the non selected bitlines B_(0,0), B_(0,1), . .. B_(0,7) of the selected byte are at the same potential of the sourceand the sources of the non-selected rows are floating (source selecttransistor T₀, T₁, . . . T_(2n), T_(2n+1) is turned off).

As it was mentioned for the array which uses the NMOS split gate cell,the use of this cell simplify the process, but it has the same problemthat the presence of the memory select transistor its relatively thickgate oxide reduces the read current.

The sustaining voltage requirements for the junctions are modest.

FIG. 7 is an electrical schematic diagram of the memory array of the OTPnonvolatile memory cell array 70. In the present invention, the One TimeProgrammable (OTP) memory array 70 of FIG. 7, is made of OTP nonvolatilememory transistor 71. The OTP nonvolatile memory cell array 70 circuitdepicted in FIG. 7 is similar to the nonvolatile memory cell array 10circuit depicted in FIG. 1 with the differences note below.

Each OTP nonvolatile memory cell array 70, has a source 72, a drain 73,and a floating gate 74. Note the absence of a control gate as innonvolatile memory cell array 10 of FIG. 1 control 15. There is nocontrol gate because this is a One Time Programmable nonvolatile memorycell array and the control gate is not needed for erase due to UV erase.

Wordlines W₀, W₁, . . . W_(2n), W_(2n+1) are used to select half of agiven row of OTP nonvolatile memory transistors 71 of the OTPnonvolatile memory cell array 70. Each of the wordlines W₀, W₁, . . .W_(2n), W_(2n+1) activates a source select transistor T₀, T₁, . . .T_(2n), T_(2n+1).

OTP nonvolatile memory cell array 70 with configuration described beforefor the PMOS cell can be used very effectively for an OTP array.

A PMOS nonvolatile memory transistors 71, which can be fabricated in astandard CMOS process without adding new steps, have been proposed usingthe logic PMOS device with the gate floating 74 as the memory device andthe NMOS logic transistor for accessing the memory. The memory cell isprogrammed to be normally on, erasing can only be done by UV erase. Thisarray can be used for One Time Programmable (OTP) memory functions.

Programming of a cell (0,0 for example) is done by applying for instance6 V to the N-well and the source S. Also, grounding bitline B_(0,0) andwordline W₀ with the source select transistor T₀ being turned on.

As explained before for the PMOS array, the channel length of the cellis adjusted so that the memory cell is in punch-through under theseconditions and the resultant channel current creates hot electrons whichare injected into the floating gate. The PMOS nonvolatile memorytransistors 71 use the standard PMOS device of a logic CMOS process withno additional steps added.

This configuration can use either the split nonvolatile memorytransistors or stacked gate nonvolatile memory transistors.

FIG. 8a is a diagram of a prior art memory cell ETOX Cell 80.

A stacked gate nonvolatile memory transistor 83 is shown in FIG. 8b. Thenovel aspect of a separate source 84 for each row separated the mirrorednonvolatile memory transistors 11 in FIG. 1.

A split gate nonvolatile memory transistor 85 is shown in FIG. 8c. Inthe split gate nonvolatile memory transistor 85, the portion of thewordline W₀, W₁, . . . W_(2n), W₂₊₁ over the diffusion area is calledthe memory select gate 86. This memory select gate 86 is some fractionof the total floating gate 87.

Both nonvolatile memory transistors, stacked and split, have the samewidth of the ETOX cell. The height of the cell with separate source S isincreased because of the need of separating the source S of one row fromthe adjacent one. The height of the split gate width is increasedbecause of the need of adding the select gate.

Using a common set of layout rules typical of a 0.25 um technology, theincrease in cell size for both the separate source or split gate cell isaround 30%. For the PMOS stacked gate nonvolatile memory transistorcell, the increase is actually less because the deep source junctionused in the ETOX cell is not needed and the channel length of thestacked gate nonvolatile memory transistor cell can also be reducedbecause because of the reduced source to drain bias used for programmingof the nonvolatile memory transistor cell.

In addition, the increase in cell area has to be weighted against theamount of area necessary for implementing all the peripheral circuits.For all the arrays described there is no need to control the erased orprogrammed threshold as needed for the ETOX cell. This reduces theamount of peripheral circuitry used for that function.

The currents required for programming selectively the PMOS nonvolatilememory transistor cells are an order of magnitudes lower than theprogramming current of the ETOX cell. This reduces the size of thecharge pumps.

In general, it can be said that the size of any of the memory arrays,including peripheral circuits, which uses the PMOS or NMOS nonvolatilememory transistor cells, either stacked or split gate, is going to bevery close to that of an ETOX array.

While embodiments and applications of this invention have been shown anddescribed, it would be apparent to those skilled in the art that manymore modifications than mentioned before are possible without departingfrom the inventive concepts herein. The invention, therefore, is not tobe restricted except in the spirit of the appended claims.

1. An array of nonvolatile memory cells arranged in a plurality of rowsa plurality of columns comprising: a substrate upon which said array isdeposited; a wordline plurality of wordlines wherein each of saidplurality of wordlines is associated with a one of said plurality ofrows in the array; a plurality of bitlines wherein each of saidplurality of bitlines is associated with one of said plurality ofcolumns in the array; a plurality of nonvolatile memory transistors,each of said nonvolatile memory transistors associated with a one ofsaid plurality of rows and a one of said plurality of columns in thearray, each one of said plurality of nonvolatile memory transistorshaving a source, a drain, a floating gate and a control gate, thecontrol gate of each one of said plurality of nonvolatile memorytransistors coupled to the one of said plurality of wordlines of saidone of said plurality of rows associated with said one of said pluralityof nonvolatile memory transistor, the drain of each one of saidplurality of nonvolatile memory transistors coupled to the one of saidplurality of bitlines of said one of said plurality of columnsassociated with said one of said plurality of nonvolatile memorytransistors, the source of each one of said plurality of nonvolatilememory being couple to the source of each of said other ones of saidplurality of nonvolatile memory transistors in said one of saidplurality of rows associated with said one of said plurality ofnonvolatile memory transistors; a plurality of source transistorswherein each one of said plurality of source transistors has a gatecoupled to a one of said plurality of wordlines, a source coupled to asource potential line, and a drain coupled to the sources of each ofsaid plurality of nonvolatile memory transistors associated with saidone of said plurality of rows associated with said wordline coupled tosaid source of said one of said plurality of source transistors; aplurality of isolation well in said substrate wherein a portion of saidplurality of nonvolatile memory transistors associated with a byte ofdata are disposed in each of said plurality of isolation wells; and aplurality of well selection transistors wherein each one of saidplurality of well selection transistors is connected to a one of saidplurality of isolation wells.
 2. An array of nonvolatile memory cellsarranged in a plurality of rows and a plurality of columns comprising: asubstrate upon which said array is deposited; a plurality of wordlineswherein each of said plurality of wordlines is associated with a one ofsaid plurality of rows in the array; a plurality of bitlines whereineach of said plurality of bitlines is associated with one of saidplurality of columns in the array; a plurality of nonvolatile memorytransistors, each of said nonvolatile memory transistors associated witha one of said plurality of rows and a one of said plurality of columnsin the array, each one of said plurality of nonvolatile memorytransistors having a source, a drain, a floating gate and a controlgate, the control gate of each one of said plurality of nonvolatilememory transistors coupled to the one of said plurality of wordlines ofsaid one of said plurality of rows associated with said one of saidplurality of nonvolatile memory transistor, the drain of each one ofsaid plurality of nonvolatile memory transistors coupled to the one ofsaid plurality of bitlines of said one of said plurality of columnsassociated with said one of said plurality of nonvolatile memorytransistors, the source of each one of said plurality of nonvolatilememory being couple to the source of each of said other ones of saidplurality of nonvolatile memory transistors in said one of saidplurality of rows associated with said one of said plurality ofnonvolatile memory transistors; a plurality of source transistorswherein each one of said plurality of source transistors has a gatecoupled to a one of said plurality of wordlines a source coupled to asource potential line, and a drain coupled to the sources of each ofsaid plurality of nonvolatile memory transistors associated with saidone of said plurality of rows associated with said wordline coupled tosaid source of said one of said plurality of source transistors; aplurality of isolation wells in said substrate wherein a portion of saidplurality of nonvolatile memory transistors associated with a byte ofdata are disposed in each of said plurality of isolation wells; and aplurality of well selection transistors wherein each one of saidplurality of well selection transistors is connected to a one of saidplurality of isolation wells.
 3. An array of one-time programmablenonvolatile memory cells arranged in a plurality of rows and a pluralityof columns comprising: a substrate upon which said array is deposited; aplurality of wordlines wherein each of said plurality of wordlines isassociated with a one of said plurality of rows in the array; aplurality of bitlines wherein each of said plurality of bitlines isassociated with one of said plurality of columns in the array; aplurality of nonvolatile memory transistors, each of said nonvolatilememory transistors associated with a one of said plurality of rows and aone of said plurality of columns in the array, each one of saidplurality of nonvolatile memory transistors having a source, a drain, afloating gate and a control gate, the control gate of each one of saidplurality of nonvolatile memory transistors coupled to the one of saidplurality of wordlines of said one of said plurality of rows associatedwith said one of said plurality of nonvolatile memory transistor, thedrain of each one of said plurality of nonvolatile memory transistorscoupled to the one of said plurality of bitlines of said one of saidplurality of columns associated with said one of said plurality ofnonvolatile memory transistors, the source of each one of said pluralityof nonvolatile memory being couple to the source of each of said otherones of said plurality of nonvolatile memory transistors in said one ofsaid plurality of rows associated with said one of said plurality ofnonvolatile memory transistors; a plurality of source transistorswherein each one of said plurality of source transistors has a gatecoupled to a one of said plurality of, a source coupled to a sourcepotential line, and a drain coupled to the sources of each of saidplurality of nonvolatile memory transistors associated with said one ofsaid plurality of rows associated with said wordline coupled to saidsource of said one of said plurality of source transistors; a pluralityof isolation well in said substrate wherein a portion of said pluralityof nonvolatile memory transistors associated with a byte of data aredisposed in each of said plurality of isolation wells; and a pluralityof well selection transistors wherein each one of said plurality of wellselection transistors is connected to a one of said plurality ofisolation wells.
 4. A substrate, comprising: a plurality of nonvolatilememory metal oxide semiconductor (MOS) transistors formed in rows andcolumns of an array; a plurality of wordlines, one or more of saidwordlines being associated with one or more of said rows; a plurality ofisolation wells, wherein one or more portions of said plurality ofnonvolatile memory MOS transistors associated with one or more portionsof data are disposed in associated one or more of said plurality ofisolation wells; a plurality of well selection transistors connected toassociated ones of said plurality of isolation wells; and a plurality ofsource transistors, one or more of said source transistors comprisinggates coupled to associated one or more of said plurality of wordlines,said source transistors comprising sources coupled to a source potentialline.
 5. The substrate of claim 4 and further comprising a plurality ofbitlines, one or more of said bitlines being associated with one or moreof said columns.
 6. The substrate of claim 5, wherein one or more ofsaid nonvolatile memory MOS transistors comprise a drain coupled toassociated ones of said bitlines.
 7. The substrate of claim 4, whereinsaid nonvolatile memory MOS transistors further comprise a source,wherein a source of a nonvolatile memory MOS transistor in a row iscoupled to sources of other nonvolatile memory MOS transistors in saidrow.
 8. The substrate of claim 4, wherein one or more of saidnonvolatile memory MOS transistors comprise a control gate coupled to anassociated one of said wordlines.
 9. The substrate of claim 4, whereinone or more of said plurality of source transistors further comprise adrain coupled to sources of nonvolatile memory MOS transistorsassociated with a row of said one or more of said plurality of rowsassociated with said associated one or more wordlines.
 10. The substrateof claim 4, wherein said array comprises a stacked array.
 11. Thesubstrate of claim 4, wherein said array comprises a split gate array.12. The substrate of claim 4, wherein said non-volatile memory MOStransistors are capable of being erased using substantially a uniformchannel erase.
 13. The substrate of claim 4, wherein said one or moreportions of data comprise one or more bytes of data.
 14. The substrateof claim 5, wherein said isolation wells comprise a plurality ofN-wells.
 15. The substrate of claim 5, wherein said isolation wellscomprise a plurality of P-wells.
 16. A method comprising: forming aplurality of nonvolatile memory metal oxide semiconductor (MOS)transistors in a substrate as an array comprising rows and columns;forming a plurality of wordlines in said substrate, one or more of saidwordlines being associated with one or more of said rows; forming aplurality of isolation wells in said substrate, wherein one or moreportions of said plurality of nonvolatile memory transistors areassociated with one or more portions of data and disposed in associatedone or more of said plurality of isolation wells; forming a plurality ofwell selection transistors in said substrate connected to associatedones of said plurality of isolation wells; and forming a plurality ofsource transistors in said substrate, one or more of said sourcetransistors comprising gates coupled to associated one or more of saidplurality of wordlines, said source transistors comprising sourcescoupled to a source potential line.
 17. The method of claim 16, andfurther comprising forming a plurality of bitlines in said substrate,one or more of said bitlines being associated with one or more of saidcolumns.
 18. The method of claim 17, wherein one or more of saidnonvolatile memory MOS transistors comprise a drain coupled toassociated ones of said bitlines.
 19. The method of claim 16, whereinsaid nonvolatile memory MOS transistors further comprise a source,wherein a source of a nonvolatile memory MOS transistor in a row iscoupled to sources of other nonvolatile memory MOS transistors in saidrow.
 20. The method of claim 16, wherein one or more of said nonvolatilememory MOS transistors comprise a control gate coupled to an associatedone of said wordlines.
 21. The method of claim 16, wherein one or moreof said source transistors further comprises a drain coupled to sourcesof nonvolatile memory MOS transistors associated with a row of said oneof said plurality of rows associated with said wordlines coupled to saidsources of said one or more of said plurality of source transistors. 22.The method of claim 16, wherein said array comprises a stacked array.23. The method of claim 16, wherein said array comprises a split gatearray.
 24. The method of claim 16, wherein said non-volatile memory MOStransistors are capable of being erased using substantially a uniformchannel erase.
 25. The method of claim 16, wherein said one or moreportions of data comprise one or more bytes of data.
 26. The method ofclaim 16, wherein said forming said plurality of said isolation wellsfurther comprises forming said plurality of isolation wells in saidsubstrate as a plurality of N-wells.
 27. The method of claim 16, whereinsaid forming said plurality of said isolation wells further comprisesforming said plurality of isolation wells in said substrate as aplurality of P-wells.
 28. A nonvolatile memory apparatus comprising: aplurality of metal oxide semiconductor (MOS) transistors formed in oneor more rows and in a plurality of isolation wells, wherein one or morewordlines are operatively associated with said one or more of said rowsand a plurality of well selection transistors are operatively associatedones of said plurality of isolation wells; and a plurality of sourcetransistors, one or more of said source transistors comprising gatescoupled to associated one or more of said plurality of wordlines, saidsource transistors comprising sources coupled to a source potentialline.
 29. The nonvolatile memory apparatus of claim 28, wherein saidplurality of metal oxide semiconductor (MOS) transistors comprises astacked array.
 30. The nonvolatile memory apparatus of claim 28, whereinsaid plurality of metal oxide semiconductor (MOS) transistors comprisesa split gate array.
 31. The nonvolatile memory apparatus of claim 28,wherein said nonvolatile memory apparatus comprises a Flash memorydevice.
 32. The nonvolatile memory apparatus of claim 28, wherein saidnonvolatile memory apparatus comprises an erasable programmable readonly memory (EPROM) memory device.
 33. The nonvolatile memory apparatusof claim 28, wherein said nonvolatile memory apparatus comprises anelectrically erasable programmable read only memory (EEPROM) memorydevice.
 34. A method for use with a nonvolatile memory apparatus, themethod comprising: selectively causing a source of at least one sourcetransistor having a gate coupled to at least one wordline toelectrically float; and selectively erasing at least one memory cellcomprising one or more metal oxide semiconductor (MOS) transistorsformed in at least one row and in at least one isolation well, whereinsaid at least one wordline is operatively associated with said at leastone row and at least one well selection transistor is operativelyassociated with said at least one isolation well.
 35. A method for usewith a nonvolatile memory apparatus, the method comprising: selectivelycausing a source of at least one source transistor having a gate coupledto at least one wordline to not electrically float; and selectivelyprogramming or reading at least one memory cell comprising one or moremetal oxide semiconductor (MOS) transistors formed in at least one rowand in at least one isolation well, wherein said at least one wordlineis operatively associated with said at least one row and at least onewell selection transistor is operatively associated with said at leastone isolation well.